With the evolving of semiconductor technologies, semiconductor dies are becoming increasingly smaller. However, more functions need to be integrated into the semiconductor dies. Accordingly, the semiconductor dies need to have increasingly greater numbers of I/O pads packed into smaller areas, and the density of the I/O pads rises quickly. As a result, the packaging of the semiconductor dies becomes more difficult, adversely affecting the yield.
Package technologies can be divided into two categories. One category is typically referred to as wafer level package (WLP), wherein dies on a wafer are packaged before they are sawed. The WLP technology has some advantages, such as greater throughput and lower cost. Further, less under-fill or molding compound is needed. However, WLP suffers drawbacks. As aforementioned, the sizes of the dies are becoming increasingly smaller, and the conventional WLP can only be fan-in type packages, in which the I/O pads of each die are limited to a region directly over the surface of the respective die. With the limited areas of the dies, the number of the I/O pads is limited due to the limitation of the pitch of the I/O pads. If the pitch of the pads is to be decreased, solder bridges may occur. Additionally, under the fixed ball-size requirement, solder balls must have a certain size, which in turn limits the number of solder balls that can be packed on the surface of a die.
In the other category of packaging, dies are sawed from wafers before they are packaged, and only “known-good-dies” are packaged. An advantageous feature of this packaging technology is the possibility of forming fan-out chip packages, which means the I/O pads on a die can be redistributed to a greater area than the die, and hence the number of I/O pads packed on the surfaces of the dies can be increased.
FIG. 1 illustrates a conventional fan-out chip package structure. Package substrate 4 includes solder balls 6 and redistribution traces 8. Redistribution traces 8 are electrically connected to pads 10 of die 2, and thus redistribute pitch P1 of pads 10 to a greater pitch P2 of solder balls 6. The resulting package has a significantly greater size and a greater pitch than die 2.
U.S. Pat. No. 7,170,152, U.S. Pat. No. 7,192,807 and U.S. Pat. No. 7,196,408 disclose other fan-out type packaging techniques. These packaging techniques suffer from a common drawback: the dies have to be aligned to their respective connecting portions with very high accuracy. Otherwise, the package may fail.
Accordingly, what is needed in the art is a packaging method having the fan-out ability, while at the same time overcoming the deficiencies of the prior art.